1. Technical Field of the Invention
The present invention relates to a voltage level converter for interfacing signals between different families of logic circuits. In particular, this invention relates to an improved voltage level converter for converting from Complimentary Metal Oxide Semiconductor (CMOS) to Positive Emitter Coupled Logic (PECL) logic levels, that is insensitive to process and temperature variations and has low power consumption.
2. Description of Related Art
Positive Emitter Coupled Logic (PECL) is used to transmit data at high speeds. PECL logic was initially implemented using bipolar devices. However these devices consumed a significant amount of power and this technology required a complex fabrication process. BICMOS devices were then introduced to improve speed and reduce power consumption. Subsequent advances in NMOS and CMOS technologies have made it possible to implement PECL in these technologies and further reduce power consumption and reduce cost. However, the logic levels of conventional CMOS logic devices and PECL logic devices are very different. This necessitates the use of special logic voltage level converters when interfacing between CMOS and PECL devices. The situation is further complicated by the increased propagation delay in the converter and lower signal fidelity of the CMOS circuitry. As PECL devices are essentially used in high-speed applications, use differential signals and operate with relatively small signal swings the voltage level converter must provide high switching speed and introduce minimal noise and signal skew. The situation is compounded by the fact that in a PECL device fabrication processes produce large variations in logic levels thereby adversely affecting the noise margin. Existing CMOS to PECL voltage level converter do not provide desired compensation for parameter variations arising out of process tolerances.
U.S. Pat. No. 5,633,602 describes a voltage converter for CMOS to PECL logic levels. This patent teaches a constant current source for providing an initial current to sustain a PECL low logic level. A voltage divider, coupled to the constant current source, stabilizes the initial current provided from the constant current source. A switchable constant current source provides an additional current to the initial current from the constant current source to sustain an ECL high logic level. A biasing means, coupled to the constant current source and the switchable constant current source, provides a voltage offset to the initial current from the constant current source and the additional current from the switchable current source. This arrangement consumes significant power owing to continuous current through the voltage divider. Also, a desired output voltage level variation tracking the supply voltage variations does not exist as in logic low state the gate to source voltage of the pull up transistor changes with voltage variation whereas its drain to source voltage remain constant. Since the compensation is particularly required when the output of the driver achieves a high logic level thus, the compensation provided by the constant current is not very effective owing to output voltage variations as a result of process parameter spreads and temperature. A further disadvantage is that the switchable constant current source (source follower) needs to be sized larger than the constant current source (pull up transistor) to achieve an adequate high logic level, resulting in increased area.